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ARM, previously known as Advanced RISC Machine, currently Acorn RISC Machine, is a computer architecture which is a member of reduced instruction set computing (RISC). ARM 7TDMI-S is 32-bit high performance and low-power consumption microprocessor basing on Von Neumann architecture. For this reason, it is dispensable architecture underlying embedded systems, tablets and smartphones.
Figure 1: Detailed Block Diagram of ARM 7TDMI-S (ARM 7TDMI-S Technical Reference Manuel 2004).
Von Neumann architecture consists of control unit, arithmetic logic unit, memory, input-output modules, and its system bus. When ARM7TDMI-S was created, it was based on Von Neumann architecture so that it has control logic and instruction decoder, 32-bit ALU, barrel shifter, TAP controller, and embedded ICE-RT macrocell. Its single data bus runs as Von Neumann’s data bus carrying both data and instructions. Memory can only be accessed by using load, swap, and store instructions. Apart from these, it provides 3-stage pipeline (ARM 7TDMI-S Technical Reference Manuel 2004).
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Intel 80386DX was introduced in 1985 as a 32-bit microprocessor, which also supports 8-bit and 16-bit, based on x86 instruction set architecture. When its first version was released, it contained 275,000 transistors (Evans 2016) and it was used as a CPU of personal computers and workstations. The amount of addressable memory in 80386DX is 4G bytes owing to its 32-bit data bus and it does not need to reset microprocessor when it switches between protected mode and real mode (Brey 1993).
Figure 2: Block Diagram of Intel 80386DX
When Von Neumann and Intel 80386DX are compared, it can be observed that they both include memory management unit, arithmetic logic unit, memory, input-output modules and data bus. When Intel 80386DX’s bus structure is analysed, it can be seen that It has a bus interface that provides a 32-bit data bus, a 3-bit address bus, and the signals which are needed to check transfers over the bus.
Intel 80386DX mainly consists of 3 sections that are Central Processing Unit (CPU), Memory Management Unit (MMU), Bus Control Interface (BCI). CPU includes barrel shifter-adder, multiply/divide, register file, decode and sequencing, and control ROM. On the other hand, MMU has 2 units that are segmentation unit and paging unit. Lastly, BCI contains request prioritizer, address driver, pipeline/bus size control, and multiplexer/transceivers. These main units are connected with internal control bus, effective address bus, dedicated ALU bus, linear address bus, and physical address bus.
On the other hand, ARM 7TDMI-S comprises CPU, EmbeddedICE microcell, EmbeddedICE TAP controller, data bus, scan chain 1, and scan chain 2. Its CPU includes instruction decoder and control logic, instruction pipeline/read data register/thumb instruction decoder, write data register, barrel shifter, 32-bit ALU, 32×8 multiplier, register bank, address register, and address incrementer. The CPU uses PC bus, incrementer bus, A bus, and B bus internally.
Intel 80386DX has been empowered with x86 instruction set architecture that the vast majority of personal computers contain. Intel x86 processor bases on complex instruction set computer (CISC) architecture that includes a number of ad hoc registers rather than considerable amount of general-purpose registers so that CISC is able to perform innumerable low-level operations in single instructions. On the other hand, ARM7 bases on 32-bit reduced instruction set computer (RISC) and 16-bit Thumb instruction set (ARM Information Center 2001). Commands which can be divided into a number of instructions are used by RISC so that it can achieve low-level operation within a clock cycle. An example of multiplication of two numbers in these systems;
MULT 2:3, 5:2
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
Figure 3: Multiplication of two numbers in CISC and RISC (Roberts n.d.)
Due to the fact that RISC has more lines of instructions, it can be understood that RISC is less efficient than CISC. However, in reality, RISC comes with numerous advantages. Owing to the fact only one clock cycle is required to execute an instruction, the program will be executed in approximately as the same proportion of time as MULT command uses. Because all the instructions are executed in one clock, RISC instructions need less transistors than the complex instructions so that RISC leaves more space for general purpose registers. By contrast, as the length of instructions is comparatively short, CISC requires less RAM (Roberts n.d.). The following formula is generally used to measure a computer’s performance;
RISC approach is to reduce the cycles per instruction (CPI) by sacrificing the number of instruction whereas CISC approach is to reduce the number of instructions by sacrificing CPI. Another difference is that RISC processors only let special load and store operations access memory which means that remained operations are based on register to register so that instruction set design is simplified (Dandamudi 2014).
Apart from RISC and CISC, Thumb was developed to hold most used instructions of 32-bit ARM instructions and it supports all the advantages of 32-bit core such as 32-bit address space, 32-bit registers, 32-bit ALU. For this reason, it provides a long branch range, strong arithmetic operations, and a large address space. Furthermore, according to the research done by ARM, when a processor runs with 16-bit memory system, Thumb code’s size approximately becomes 65 percent of ARM code and the system gains 160 percent of the performance of ARM code (ARM 7TDMI-S Technical Reference Manuel 2004).
Figure 4: Code Size Comparison Between ARM, Thumb-2 and Thumb (The ARM Architecture n.d.)
The Internal Architecture of 80386DX is divided into 3 sections which are Central Processing Unit (CPU), Memory Management Unit (MMU), and Bus Interface Unit (BIU). In addition, CPU is further divided into 2 sections that are Execution Unit (EU) and Instruction Unit (IU). EU contains 16 registers that half of them are for general purpose and rest of them are special purpose. General purpose registers are accessed and are designed to keep 8, 16, or 32-bit data whereas segment registers include a segment address in real mode operation and they a selector in protected mode operation. On the other hand, the house keeping registers comprise a 32-bit flag register (EFLAGS) and a 32-bit instruction pointer (EIP) (Brey 1993).
Figure 5: Internal structure of Intel 80386 demonstrating general-purpose, segment, and housekeeping registers (INTEL 80386 PROGRAMMER’s REFERENCE MANUAL 1986).
When ARM 7TDMI-S is examined, it can be seen that ARM 7TDMI-S processor is based on Von Neumann Architecture. In addition, it uses the Advanced Microcontroller Bus Architecture (AMBA) and this architecture is divided into 2 system buses which are the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ARM 7TDMI-S processor includes 32-bit Arithmetic Logic Unit (ALU), 32-bit Booth multiplier, Barrel shifter, Control unit and 32-bit of 37 registers where 31 of those are for general-purpose and the rest is for status registers such as Instruction Register (IR), Memory Address Register (MAR), and Priority Encoder (PE).
Figure 6: Internal Architecture of ARM 7TDMI-S (ARM Information Center 2001).
Fast local storage for constantly used code and data can be achieved by using a cache memory system. The microprocessor obtains faster memory access and significantly reduced majority of traffic on system bus.
Intel 80386DX does not have cache on chip unlike 80486. However, it supports cache off chip. Cache controller on 80386DX has been inherited from 80385 and it supports full potential performance features. One of them is that, it supports a 32kb cache memory adjusted as either 2-way set associative or direct mapping. Secondly, it offers management logic and integrated cache directory. Thirdly, cache coherency is guaranteed by bus watching. Moreover, non-cacheable accesses are supported and according to Dhrystone benchmark, it can achieve 95 percent of hit rate (80386 Hardware Reference Manual 1986).
ARM 7TDMI-S does not include cache internally. However, it uses 3-stage pipeline in order to increase the pace of the flow of the instructions that go through the processor. Thus, a number of operations are enabled to occur simultaneously. These 3-stage are Fetch, Decode, and Execute respectively (ARM 7TDMI-S Technical Reference Manuel 2004).
Figure 7: 3-stage pipeline in ARM7TDMI-S (Arm Processors 2018).
As it was mentioned before, Intel 80386DX is divided into 3 sections that are CPU, MMU, and BIU.
Figure 8: InternalSections of 80386DX (Smith 2016).
BIU is an interface to the external devices. It has 32-bit data bus and a 3-bit address bus. In addition, it contains signals to check transmissions over the bus structure. Its Request Prioritzer unit analyses priority of different bus requests and it can be said that this has a control over the access of the bus. Moreover, BIU of Intel 80386DX supports 8-bit, 16-bit and 32-bit data transmissions. It also launches address pipelining when Next Address (NA) is received. Finally, it provides dynamic bus sizing (Smith 2016).
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When ARM 7TDMI-S is examined, it can be observed that it provides Advanced Microcontroller Bus Architecture (AMBA) which demonstrates a way for the interconnection and management of functional blocks. It is divided into three sections which are Advanced System Bus (ASB), Advanced High-performance Bus (AHB), and Advanced Peripheral Bus (APB) (AMBA Bus Architecture 2001). AHB provides high performance, pipelined operation, multiple bus masters and burst transfers whereas ASB is capable of everything that AHB has except for burst transfers. On the other hand, APB has been designed for low power, latched address and control, suitable for many peripherals (ARM Tutorial | ARM Bus Technology,Memory And Peripherals n.d.).
Figure 9: ARM Bus Architecture (ARM Tutorial | ARM Bus Technology,Memory And Peripherals n.d.)
Intel 80386DX includes Memory Management Unit (MMU) having Paging Unit (PU). The main purpose of MMU is to convert logical addresses into physical addresses that indicates a physical memory location. For instance, in spite of the fact that memory location B0000H is being accessed by a program with an instruction, it can be observed that the actual physical address could be any other location with the help of paging. Intel 80386DX contains descriptors and selectors in which descriptors are used to describe or to locate a memory segment with a series of 8 bytes whereas selectors index a descriptor from the table of descriptors. The descriptors in Intel 80386DX benefit from 32-bit base addresses and 20-bit limit so that it becomes capable of addressing 4GB memory space with the 32-bit base address. In addition, segment length limit varies with the value of granularity bit (G). If G is set to 0, then the length becomes 1MB otherwise it is set to 1 and it becomes 4gb length. Selectors uses 13-bit in order to access a descriptor that means the maximum number of descriptors that each table can contain is 8,192 descriptors. As each segment can have 4GB length, the number of accessible segments becomes 16,384 when 2 descriptor tables are used. That allows Intel 80386dx to have 64TB of virtual memory when it is needed (Brey 1993).
Figure 10: Descriptors Used for Applications Code and Data Segments (INTEL 80386 PROGRAMMER’s REFERENCE MANUAL 1986).
In Intel 80386DX, the memory is divided into four 8-bit-wide sections called memory banks that can contains at most 1GB memory. This allows the system to have a direct access to words, bytes, or double words.
Figure 11: The Memory Map of the 80386 Microprocessor (The Memory Map Of Intel 80386 2015).
Intel 80386DX provides paging mechanism that allows logical address to be placed into any physical memory page created by paging mechanism. The length of memory page in Intel 80386DX is 4KB. In addition, there are three core units in page mechanism which are page directory, page table, and physical memory page. The page directory is capable of containing at most 1024 page translation tables that are used to convert from logical address to physical address. Moreover, it is located in the memory and accessed by the page descriptor address register. When Page table is examined, it can be observed that it has 1024 physical page addresses. The main differences between page directory and page table is that while pate directory contains physical address of a page table, page table includes exact physical address of a 4KB memory page.
By contrast, when ARM 7TDMI-S is examined, it can be seen that it does not include MMU and its architecture is based on Von Neumann architecture with a 32-bit data bus that carries both instruction and data. The data in memory can only be accessed by load, swap, and store instructions. In addition, it provides 4 memory cycle that are nonsequential, sequential, internal, and coprocessor register transfer. Memory is observed as a linear sequence of bytes in ascending order. For instance, the first word is in bytes from 0 to 3, the second is in bytes from 4 to 7 and the third is in bytes from 8 to 11. ARM 7TDMI-S processes data in memory by using 2 different types of formats that are big-endian format and little-endian format. In big-endian format, the least significant byte is stored at the highest-numbered byte and the most significant byte is stored at the lowest-numbered byte whereas in little-endian format, the least significant and the most significant byte are stored at the lowest-numbered byte and the highest-numbered byte respectively (ARM 7TDMI-S Technical Reference Manuel 2004).
Figure 12: Big-endian addresses of bytes within words (ARM 7TDMI-S Technical Reference Manuel 2004).
Figure 13: Little-endian addresses of bytes within words (ARM 7TDMI-S Technical Reference Manuel 2004).
Intel 80386DX includes 64KB I/O space when isolated I/O is implemented. IN and OUT instructions transfer I/O data between I/O devices and the microprocessor. In addition, 80386DX takes the advantage of a 32-bit wide I/O system divided into 4 banks similar to memory banks. As it uses external memory space for I/O, it does not lose any memory space. Moreover, it is able to transfer 32,16, or 8-bit data at a time. On the other hand, it supports memory-mapped I/O where I/O devices can be placed in memory (INTEL 80386 PROGRAMMER’s REFERENCE MANUAL 1986).
Figure 14: Memory-Mapped I/O in Intel 80386DX (INTEL 80386 PROGRAMMER’s REFERENCE MANUAL 1986).
In ARM 7TDMI-S, all I/O operations are memory-mapped. In addition, it uses Arm Peripheral Bus (APB) that is optimized to minimize power and reduced interface complexity. It uses APB to interface peripherals that does not need high performance.
Intel 80386DX does not include parallelism. However, it has been empowered with multiprocessing. When it switches to virtual mode, it becomes able to execute multiple applications by using the technique called time-slicing. Amount of time is set to each task by operating system and after that time, operating system switches the task.
Similarly, due to the fact that Single Instruction Multiple Data (SIMD) has been introduced with ARM v6, ARM 7TDMI-S does not support parallelism because it is based on ARM v4T.
As both systems are single core processors, they are not able to take advantage of parallelism. However, they empower themselves by using pipelining.
- Push: push data onto stack
- Mov: copies data from one location to another
- Nop: no operation
- Pop: pop data from stack
- Ret: return from procedure
- Sub: subtraction
- Cdqe: convert double-word to quad-word
- Lea: load effective address
- Add: add
- Cmp: complement carry flag
- Jle: It performs a signed comparison jump after a cmp if the destination operand is less than or equal to the source operand.
- Jl: It performs a signed comparison jump after a cmp if the destination operand is less than the source operand.
- Call: It pushes the return address on stack and it also changes EIP to the call destination.
- Jmp: jump
- Leave: leave stack frame
- Ret: pops the return address off the stack and returns control to that location.
- Jge: It performs a signed comparison jump after a cmp if the destination operand is greater than or equal to the source operand.
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